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the PA
What is verilator?
Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code.
These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper file, to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators.
how to install verilator?
verilator manual
示例: 双控开关
vscode HDL插件使用
服务器的图形化显示转发
Do HDLBits
Verilog的一些原则
除 wire 类型外,另外一种常用的数据类型,一般表示寄存器类型数据,不过并不绝对,记住一条原则:在 always 块内被赋值的信号应定义成 reg 型,用 assign 语句赋值的信号应定义成 wire 型。
When you have multiple assign statements, the order in which they appear in the code does not matter. Unlike a programming language, assign statements ("continuous assignments") describe connections between things, not the action of copying a value from one thing to another.
One potential source of confusion that should perhaps be clarified now: The green arrows here represent connections between wires, but are not wires in themselves. The module itself already has 7 wires declared (named a, b, c, w, x, y, and z). This is because
input
and output
declarations actually declare a wire unless otherwise specified. Writing input wire a
is the same as input a
. Thus, the assign
statements are not creating wires, they are creating the connections between the 7 wires that already exist.An
assign
statement drives a wire (or "net", as it's more formally called) with a value. This value can be as complex a function as you want, as long as it's a combinational (i.e., memory-less, with no hidden state) function. An assign
statement is a continuous assignment because the output is "recomputed" whenever any of its inputs change, forever, much like a simple logic gate.- 作者:liamY
- 链接:https://liamy.clovy.top/article/103652d0-85b7-8043-9f78-c35989b26828
- 声明:本文采用 CC BY-NC-SA 4.0 许可协议,转载请注明出处。